Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 137)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 118
7.1.24 IPMC Outlet Temperature Sensor Status Register - 0x1E
7.1.25 FRAM Page Access Register - 0x20
4 Reserved 0 RO R/W
5 Reserved 0 RO R/W
7:6 Reserved 0x0 RO RO
Table 7-23 IPMC Inlet Temperature Sensor Status Register - 0x1D (continued)
Bit # Description Default LPC Access I2C Access
Table 7-24 IPMC Outlet Temperature Sensor Status Register - 0x1E
Bit # Description Default LPC Access I2C Access
0 Reserved 0 RO R/W
1 Reserved 1 RO R/W
2 Reserved 0 RO R/W
3 Reserved 0 RO R/W
4 Reserved 0 RO R/W
5 Reserved 0 RO R/W
7:6 Reserved 0x0 RO RO
Table 7-25 FRAM Page Access Register - 0x20
Bit # Description Default LPC Access I2C Access
3:0 FRAM Page Select 0x00 R/W -
0x0: Page 0 (access first 64K block of
FRAM) to
0xF: Page 15 (access last 64K block
of FRAM)