Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 149)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 130
7.3.1.3 Interrupt Enable Register (IER)
This register enables four types of interrupts which independently activate the int signal and
set a value in the Interrupt Identification Register. Each of the four interrupt types can be
disabled by resetting the appropriate bit of the IER register. Similarly, by setting the appropriate
bits, selected interrupts can be enabled.
Table 7-46 Interrupt Enable Register (IER), if DLAB=0
IO Address: Base +1
Bit # Description Default Access
0 Receive data interrupt enable/disable:
1: receive data interrupt enabled
0: receive data interrupt disabled 0 R/W
1 Transmitter holding register empty (THRE)
interrupt enable/disable
1: THRE interrupt enabled
0: THRE interrupt disabled 0 R/W
2 Receiver line status interrupt enable/disable
1: receiver line status interrupt enabled
0: receiver line status interrupt disabled 0 R/W
3 Modem status interrupt enable/disable:
1: modem status interrupt enabled
0: modem status interrupt disabled 0 R/W
7:4 Reserved 0 R