Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 156)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 137
7.3.1.8 Line Status Register (LSR)
This register provides status information to the processor concerning the data transfers. Bits 5
and 6 are showing information about the transmitter section. The rest of the bits contain
information about the receiver.
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break
interrupt, show the error status of the character that has just been received. In FIFO mode,
these three bits of status are stored with each received character in the FIFO. LSR shows the
status bits of the character at the top of the FIFO. When the character at the top of the FIFO has
errors, the LSR error bits are set and are not cleared until software reads LSR, even if the
character in the FIFO is read and a new character is now at the top of the FIFO.
4 Local loop back diagnostic control
When loop back is activated: Transmitter TXD
is set high. Receiver RXD is disconnected.
Output of Transmitter Shift register is looped
back into the receiver shift register input.
Modem control inputs are disconnected
Modem control outputs are internally
connected to modem control inputs. Modem
control outputs are forced to the inactive
(high) levels:
1: Loop back mode activated
0: Normal operation 0 R/W
5 Autoflow control enable (AFE):
1: Autoflow control enabled (auto-RTS# and
auto-CTS# or auto-CTS# only enabled)
0: Autoflow control disabled 0 R/W
7:6 Reserved 0 R
Table 7-52 Modem Control Register (MCR) (continued)
IO Address: Base +4
Bit # Description Default Access