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Table 7-35, Super io lpc control register, Table 7-36 – Artesyn iVPX7225 Installation and Use (April 2015) User Manual

Page 143: Fpga registers

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FPGA Registers

iVPX7225 Installation and Use (6806800S11C)

124

Table 7-35 Super IO LPC Control Register

Index Address: 0x28

Bit #

Description

Default

Access

0

LPC Bus Wait States:
1: Long wait states (sync 6)

1

LPC: R

7:1

Reserved

0

LPC: R

Table 7-36 Global Super IO SERIRQ and Pre-divide Control Register

Index Address: 0x29

Bit #

Description

Default

Access

0

SERIRQ enable:
0: disabled. Serial interrupts disabled.
1: enabled. Logical devices participate in
interrupt generations.

0

LPC: R/W

1

SERIRQ Mode:
1: Continuous Mode

1

LPC: R

3:2

UART Clock pre-divide
00: divide by 1
01: divide by 8
10: divide by 26 (CLK_UART is 48 MHz)
11: Reserved

Note: the UART clock is fixed at 48MHz. The
default value should not be changed.

10

LPC: R/W

7:4

Reserved

0

LPC: R

See also other documents in the category Artesyn Equipment: