27 post code latch register - 0x28, 28 bios boot status register - 0x2c, 2 fpga sio – Artesyn iVPX7225 Installation and Use (April 2015) User Manual
Page 139: Table 7-27, Post code latch register - 0x28, Table 7-28, Bios boot status register - 0x2c, Fpga registers
FPGA Registers
iVPX7225 Installation and Use (6806800S11C)
120
7.1.27 POST Code Latch Register - 0x28
7.1.28 BIOS Boot Status Register - 0x2C
7.2
FPGA SIO
Table 7-27 POST Code Latch Register - 0x28
Bit #
Description
Default
LPC Access
I2C Access
7:0
Latch and hold POST code data when
watchdog timer reset is asserted. Register
is cleared to all zero upon power on reset
and when register is written with any data
0x00
R/WTC
RO
Table 7-28 BIOS Boot Status Register - 0x2C
Bit #
Description
Default
LPC Access
I2C Access
7:0
Writing pattern 0x5D indicates BIOS
booted successfully. Register is cleared to
0x00 upon platform reset.
0x00
R/W
-
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