8 watchdog control register - 0x09, Table 7-8, Watchdog control register - 0x09 – Artesyn iVPX7225 Installation and Use (April 2015) User Manual
Page 123: Fpga registers
FPGA Registers
iVPX7225 Installation and Use (6806800S11C)
104
7.1.8
Watchdog Control Register - 0x09
Table 7-8 Watchdog Control Register - 0x09
Bit #
Description
Default
LPC Access
I2C Access
3:0
Length of Watchdog Timer. The read access will
not show the correct data until write data is
loaded into watchdog timer (to load, set bit 5
=
1
during write).
0xF
R/W
-
0000: 16 ms
0001: 32 ms
0010: 64 ms
0011: 128 ms
0100: 256 ms
0101: 512 ms
0110: 1 s
0111: 2 s
1000: 4 s
1001: 8 s
1010: 16 s
1011: 32 s
1100: 1 min
1101: 2 min
1110: 4 min
1111: 8 min
4
Watchdog Enable
1
R/W
-
0: Watchdog disabled.
1: Watchdog enabled. It is also auto enabled after
power on reset and soft reset.
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