Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 74)

Functional Description
iVPX7225 Installation and Use (6806800S11C) 55
4.11 GPIO
iVPX7225 provides eight user-defined GPIO pins routed from the PCH to the VPX backplane P2
connector.
4.12 SMBus
The board supports a minimum of 2Kb VPD EEPROM attached to the PCH-mastered SMBus.
Although available for VPD or general use, this EEPROM is not programmed by the factory.
IPMC FRU Data is used in lieu of Vital Product Data in this application.
4.13 Boot Flash
iVPX7225 provides two SPI Flash devices, each capable of storing Flash Descriptor, Intel ME
firmware, and BIOS images. The SPI Flash devices support a clock rate of up to 50 MHz.
The SPI Flash devices are programmed to contain identical boot images for Crisis Recovery
purposes, in the event the primary boot image is inadvertently corrupted.
4.14 NAND Flash
iVPX7225 supports a 4 GB of on-board user NAND Flash. It is designed to support 8GB for
future factory builds. The NAND Flash is accessible via PCH USB Port8 and the
SiliconMotionSM3252 High Speed USB 2.0 Flash Memory Controller.
4.15 FRAM
The board provides a 1 MB reset/power-cycle persistent indefinitely-writable storage. The
FRAM is controlled by the iVPX7225 FPGA and is accessible via PCH LPC interface. FRAM is
mapped as 64k-byte window in system I/O space at 0xFE800000. FRAM pages are selected via
an FPGA register.