Fpga registers, 1 fpga registers, 1 blade revision register - 0x00 – Artesyn iVPX7225 Installation and Use (April 2015) User Manual

Page 119: Table 7-1, Blade revision register - 0x00, Chapter 7, fpga registers, Chapter 7

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Chapter 7

iVPX7225 Installation and Use (6806800S11C)

100

FPGA Registers

7.1

FPGA Registers

This section contains the description and details of the iVPX7225 FPGA local registers. FPGA
registers are mapped in I/O space 0x100 + register offset for host access and at I2C address
0x71 for IPMC access.

7.1.1

Blade Revision Register - 0x00

Default values in the register descriptions below indicate the values after board power on.

Table 7-1 Blade Revision Register - 0x00

Bit #

Description

Default

LPC Access

I2C Access

3:0

Artwork/Hardware Version

0x0: Rev 1.0
0x1: Rev 1.1
0x2: Rev 1.2
0x3: Rev 1.3

7:4

Variant Type

0xA: Air-cooled variant.
0xC: Conduction-cooled variant.