Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 152)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 133
7.3.1.5 FIFO Control Register (FCR)
FCR is a write-only register that is located at the same address as the IIR (IIR is a read-only
register). FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver
FIFOs, and sets the receiver FIFO trigger level.
0b0010 3 Transmit
FIFO Data
Request Non-FIFO mode:
Transmit Holding
Register Empty Reading the IIR Register
(if the source of the
interrupt) or writing into
the Transmit Holding
Register.
0b0000 4 Modern
Status Clear to Send, Data
Set Ready, Ring
Indicator, Received
Line Signal Detect Reading the modem
status register
Table 7-49 Interrupt Identification Register Decode (continued)
Interrupt ID Interrupt Set/Reset Function
3:0 Priority Type Source Reset Control
Table 7-50 FIFO Control Register (FCR)
IO Address: Base + 2
Bit # Description Default Access
0 FIFO enable/disable:
1: Transmitter and Receiver FIFO enabled
0: FIFO disabled 0 W
1 Receiver FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset (bit is self-clearing)
0: No effect 0 W
2 Transmit FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset (bit is self-clearing)
0: No effect 0 W
3 Receiver/Transmitter ready. Not supported. 0 W
5:4 Reserved 0 W