Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 151)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 132
5;4 Reserved 0 R
7:6 FIFO Mode Enable bits:
00: Default mode
01: Reserved
10: Reserved
11: FIFO mode 0 R
Table 7-49 Interrupt Identification Register Decode
Interrupt ID Interrupt Set/Reset Function
3:0 Priority Type Source Reset Control
0b0001 - None No Interrupt is
pending -
0b0110 1 Receiver
Line Status Overrun Error, Parity
Error, Framing Error,
Break Interrupt. Reading the Line Status
Register.
0b0100 2 Received
Data
Available Non-FIFO mode:
Receive Buffer is full. Non-FIFO mode: Reading
the Receiver Buffer
Register.
FIFO mode: Trigger
level was reached. FIFO mode: Reading
bytes until Receiver FIFO
drops below trigger level
or setting RESETRF bit in
FCR register.
0b1100 Character
Timeout
indication FIFO Mode only: At
least 1 character is in
receiver FIFO and
there was no activity
for a time period. Reading the Receiver FIFO
or setting RESETRF bit in
FCR register
Table 7-48 Interrupt Identification Register (IIR) (continued)
IO Address: Base +2
Bit # Description Default Access