Rainbow Electronics DS26504 - Manual (Page 82)

DS26504 T1/E1/J1/64KCC BITS Element
82 of 128
The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. See the Transmit Line Build-Out Control (TLBC) register for details.
13.3.1 Transmit Short-Circuit Detector/Limiter
The DS26504 has an automatic short-circuit limiter that limits the source current to 50mA (RMS) into a
1
W load. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (SR1.2) provides a
real-time indication of when the current limiter is activated. If the current limiter is disabled, TCLE will
indicate that a short-circuit condition exists. Status Register SR1.2 provides a latched version of the
information, which can be used to activate an interrupt when enable via the IMR1 register. When set low,
the TPD bit (LIC1.0) will power-down the transmit line driver and tri-state the TTIP and TRING pins.
13.3.2 Transmit Open-Circuit Detector
The DS26504 can also detect when the TTIP or TRING outputs are open circuited. TOCD (SR1.1) will
provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the
information (SR1.1), which can be used to activate an interrupt when enabled via the IMR1 register.
13.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS26504 can transmit the 2.048MHz square-wave synchronization clock. To transmit the 2.048MHz
clock, when in E1 mode, set the mode configuration bits in the Mode Configuration Register (MCREG).
13.4 MCLK Pre-Scaler
A 2.048MHz x N (where N = 1 to 4), 1.544MHz x N (where N = 1 to 4), or 12.8MHz (available in CPU
interface mode only) clock must be applied to MCLK. A pre-scaler (divide by 2, 4, or 8) and PLLs are
selected to product an internal 2.048MHz or 1.544MHz clock. ITU specification G.703 requires an
accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for
T1 interfaces. A pre-scaler divides the 16.384MHz, 12.8MHz, 8.192MHz, or 4.096MHz clock down to
2.048MHz. An on-board PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate
for T1 applications. Setting JACKS (LIC2.3) to a logic 0 bypasses this PLL.
13.5 Jitter Attenuator
The DS26504’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit
(LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The
32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in
Figure 13-10 and Figure 13-11 . The jitter attenuator can be placed in either the receive path or the
transmit path by appropriately setting or clearing the JAS bit (LIC1.3). The jitter attenuator can also be
disabled (in effect, removed) by setting the DJA bit (LIC1.1). Either the recovered clock from the
clock/data recovery block or the clock applied at the TCLK pin is adjusted to create a smooth jitter-free
clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming
jitter exceeds either 120UI
P-P
(buffer depth is 128 bits) or 28UI
P-P
(buffer depth is 32 bits), then the