Rainbow Electronics DS26504 - Manual (Page 2)

DS26502 T1/E1/J1/64KCC BITS Element
2 of 128
TABLE OF CONTENTS
1. FEATURES
............................................................................................................................ 7
1.1 G ENERAL .................................................................................................................................. 7
1.2 L INE I NTERFACE ........................................................................................................................ 7
1.3 J ITTER A TTENUATOR (T1/E1 M ODES O NLY )................................................................................ 7
1.4 F RAMER /F ORMATTER ................................................................................................................. 8
1.5 T EST AND D IAGNOSTICS ............................................................................................................. 8
1.6 C ONTROL P ORT ......................................................................................................................... 8
2. SPECIFICATIONS COMPLIANCE
............................................................................... 9
3. BLOCK DIAGRAMS
......................................................................................................... 11
4. PIN FUNCTION DESCRIPTION
................................................................................... 14
4.1 T RANSMIT PLL ........................................................................................................................ 14
4.2 T RANSMIT S IDE ....................................................................................................................... 14
4.3 R ECEIVE S IDE ......................................................................................................................... 15
4.4 C ONTROLLER I NTERFACE ......................................................................................................... 16
4.5 JTAG...................................................................................................................................... 20
4.6 L INE I NTERFACE ...................................................................................................................... 21
4.7 P OWER ................................................................................................................................... 21
5. PINOUT
................................................................................................................................. 22
6. HARDWARE CONTROLLER INTERFACE
............................................................ 25
6.1 T RANSMIT C LOCK S OURCE ....................................................................................................... 25
6.2 I NTERNAL T ERMINATION ........................................................................................................... 25
6.3 L INE B UILD -O UT ...................................................................................................................... 26
6.4 R ECEIVER O PERATING M ODES ................................................................................................. 27
6.5 T RANSMITTER O PERATING M ODES ........................................................................................... 27
6.6 MCLK P RE -S CALER ................................................................................................................ 28
6.7 P AYLOAD C LOCK O UTPUT ........................................................................................................ 28
6.8 O THER H ARDWARE C ONTROLLER M ODE F EATURES .................................................................. 29
7. PROCESSOR INTERFACE
........................................................................................... 30
7.1 P ARALLEL P ORT F UNCTIONAL D ESCRIPTION .............................................................................. 30
7.2 SPI S ERIAL P ORT I NTERFACE F UNCTIONAL D ESCRIPTION .......................................................... 30
7.2.1 Clock Phase and Polarity ..................................................................................................................... 30
7.2.2 Bit Order ............................................................................................................................................... 30
7.2.3 Control Byte ......................................................................................................................................... 30
7.2.4 Burst Mode........................................................................................................................................... 30
7.2.5 Register Writes..................................................................................................................................... 31
7.2.6 Register Reads .................................................................................................................................... 31
7.3 R EGISTER M AP ........................................................................................................................ 32
7.3.1 Power-Up Sequence ............................................................................................................................ 34
7.3.2 Test Reset Register ............................................................................................................................. 34
7.3.3 Mode Configuration Register ............................................................................................................... 35
7.4 I NTERRUPT H ANDLING .............................................................................................................. 37
7.5 S TATUS R EGISTERS ................................................................................................................. 37
7.6 I NFORMATION R EGISTERS ........................................................................................................ 38
7.7 I NTERRUPT I NFORMATION R EGISTERS ....................................................................................... 38