Rainbow Electronics DS26504 - Manual (Page 37)

DS26504 T1/E1/J1/64KCC BITS Element
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Register Name: TPCR2
Register Description: Transmit PLL Control Register 2
Register Address: 0Ah
Bit
# 7 6 5 4 3 2 1 0
Name — — — — — — TPLLOFS2 TPLLIFS2
Default 0 0
Bit 0: Transmit Clock Source Select (TPLLOFS2). This bit, along with TPLLOFS0 (TPCR1.7) and TPLLOFS1
(TPCR1.6), is used to indicate the reference frequency being input to the TX PLL. See the table in TPCR1 register description.
Bit 1: Transmit Clock Source Select (TPLLIFS2). This bit, along with TPLLIFS0 (TPCR1.4) and TPLLIFS1 (TPCR1.3), is
used to the frequency being output from the TX PLL. See the table in TPCR1 register description.
Bits 2 to 7: Unused
7.4 Interrupt Handling
Various alarms, conditions, and events in the DS26504 can cause interrupts. For simplicity, these are all
referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts.
Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an
interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only sources of
interrupts in the DS26504. On power-up, all writeable registers are automatically cleared. Because bits in
the IMRx registers must be set = 1 to allow a particular event to cause an interrupt, no interrupts can
occur until the host selects which events are to product interrupts. As there are potentially many sources
of interrupts on the DS26504, several features are available to help sort out and identify which event is
causing an interrupt. When an interrupt occurs, the host should first read the IIR register (interrupt
information register) to identify which status register(s) is producing the interrupt. Once that is
determined, the individual status register or registers can be examined to determine the exact source.
Once an interrupt has occurred, the interrupt handler routine should clear the IMRx registers to stop
further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt
hander routine should restore the state of the IMRx registers.
7.5 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the
appropriate bit in a status register will be set to a one. All the status registers operate in a latched fashion,
which means that if an event or condition occurs, a bit is set to a one. It remains set until the user reads
that bit. An event bit is cleared when it is read and it is not set again until the event has occurred again.
Condition bits such as RLOS remain set if the alarm is still present.
The user always precedes a read of any of the status registers with a write. The byte written to the register
informs the DS26504 which bits the user wishes to read and have cleared. The user writes a byte to one of
these registers, with a one in the bit positions he or she wishes to read, and a zero in the bit positions he or
she does not wish to obtain the latest information on. When a one is written to a bit location, the read
register is updated with the latest information. When a zero is written to a bit position, the read register is
not updated and the previous value is held. A write to the status registers is immediately followed by a
read of the same register. This write-read scheme allows an external microcontroller or microprocessor to