Rainbow Electronics DS26504 - Manual (Page 126)

DS26504 T1/E1/J1/64KCC BITS Element
126 of 128
Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode
TSER
TS_8K_4 1
tD2
tHD
tSU
TS_8K_4 2
tSU
t
F
t
R
TCLK
t
t
CL
t
CH
CP
TX CLOCK 3
PLL_OUT
tD3
RCLK, JA CLOCK 4
(REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, Figure 3-3 .)
NOTE 1: TS_8K_4 IN OUTPUT MODE.
NOTE 2: TS_8K_4 IN INPUT MODE.
NOTE 3: TX CLOCK IS THE INTERNAL CLOCK THAT DRIVES THE TRANSMIT SECTION. THE
SOURCE OF THIS SIGNAL DEPENDS ON THE CONFIGURATION OF THE TRANSMIT PLL. IF TX
CLOCK IS GENERATED BY THE TRANSMIT PLL (CONVERSION FROM ANOTHER CLOCK RATE)
THEN THE USER SHOULD OUTPUT THAT SIGNAL ON THE PLL_OUT PIN AND USE THAT SIGNAL
TO REFERENCE TSER AND TS_8K_4 IF TS_8K_4 IS IN THE INPUT MODE.
NOTE 4: RCLK (THE RECOVERED LINE CLOCK) AND JA CLOCK (AN INTERNAL CLOCK DERIVED
FROM MCLK) MAY BE SELECTED AS THE SOURCE FOR THE TRANSMIT PLL OR USED
UNCONVERTED FOR TX CLOCK.