Rainbow Electronics DS26504 - Manual (Page 31)

DS26504 T1/E1/J1/64KCC BITS Element
31 of 128
are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining
data will be lost. If CS is removed before all 8 bits of data are written to the part, no write access will
occur and the target register will not be updated.
Note: During a Burst-Read access, data must be fetched internally to the part as the LSB of the previous
byte is transmitted out. If this pre-fetch read access occurs to a Clear-On-Read register or a FIFO register
address, and the Burst access is terminated without reading this byte out of the port, the data will be lost
and/or the register cleared. Users should not terminate their Burst Read accesses at the address byte
proceeding a Clear-On-Read register or a FIFO register. Data loss could occur due to the internal pre-
fetch operation performed by the interface.
7.2.5 Register Writes
The register write sequence is shown in the functional timing diagrams in Section
18 . After a CS, the bus
master transmits a write control byte containing the R/ W bit, the target register address, and the Burst bit.
These two control bytes will be followed by the data byte to be written. After the first data byte, if the
Burst bit is set, the DS26504 auto-increments its address counter and writes each byte received to the next
higher address location. After writing address FFh, the address counter rolls over to 00h and continues to
auto-increment.
7.2.6 Register Reads
The register read sequence is shown in Section
18 . After a CS, the bus master transmits a read control
byte containing the R/ W bit, the target register address, and the Burst bit. After these two control bytes,
the DS26504 responds with the requested data byte. After the first data byte, if the Burst bit is set, the
DS26504 auto-increments its address counter and transmits the byte stored in the next higher address
location. Note the warning mentioned above, as data loss could potentially occur due to the data pre-fetch
that is required to support this mode. After reading address FFh, the address counter rolls over to 00h and
continues to auto-increment.