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Controller interface, Ontroller, Nterface – Rainbow Electronics DS26504 User Manual

Page 16

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DS26504 T1/E1/J1/64KCC BITS Element

16 of 128

NAME TYPE

FUNCTION

RAIS O

Receive Alarm Indication Signal
T1 Mode: Toggles high when the receive Blue Alarm is detected.
E1 Mode: Toggles high when the receive AIS is detected.
64KCC Mode: This pin is in a high-impedance state.
6312kHz Mode: This pin is in a high-impedance state.

4.4 Controller Interface

NAME TYPE

FUNCTION

INT/

JACKS

I/O

Active-Low Interrupt/Jitter Attenuator Clock Source Select 1

INT

: Flags host controller during events, alarms, and conditions defined in the

status registers. Active-low open-drain output.

JACKS: Hardware Mode: JA Clock Select. Set this pin high for T1 mode
operation when either a 2.048MHz, 4.096MHz, 8.192MHz, or 16.382MHz
signal is applied at MCLK.

TMODE1 I

Transmit Mode Select 1. In Hardware Mode (BIS[1:0] = 11), this bit is used to
configure the transmit operating mode.

TMODE2 I

Transmit Mode Select 2. In Hardware Mode (BIS[1:0] = 11), this bit is used to
configure the transmit operating mode.

TSTRST I

Tri-State Control and Device Reset. A dual-function pin. A zero-to-one
transition issues a hardware reset to the DS26504 register set. Configuration
register contents are set to the default state. Leaving TSTRST high tri-states all
output and I/O pins (including the parallel control port). Set low for normal
operation. Useful for in-board level testing.

BIS[1:0] I

Bus Interface Mode Select 1, 0. These bits select the processor interface mode
of operation.

BIS[1:0] : 00 = Parallel Port Mode (Multiplexed)
01 = Parallel Port Mode (Nonmultiplexed)

10 = Serial Port Mode

11 = Hardware Mode

AD[7]/

RITD

I/O

Data Bus D[7] or Address/Data Bus AD[7]/Receive Internal Termination
Disable
A[7]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus
D[7].

AD[7]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[7].

RITD: In Hardware Mode (BIS[1:0] = 11), it disables the internal receive
termination.