Rainbow Electronics DS26504 - Manual (Page 43)

DS26504 T1/E1/J1/64KCC BITS Element
43 of 128
Register Name:
T1CCR
Register Description: T1 Common Control Register
Register Address: 07h
Bit #
7 6 5 4 3 2 1 0
Name — — — TRAI-CI TAIS-CI — PDE —
Default 0 0 0 0 0 0 0 0
HW
Mode
0 0 0 0 0 0 0 0
Bits 0, 2, 5, 6, 7: Unused, must be set = 0 for proper operation.
Bit 1: Pulse-Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for
violations of these, which are required by ANSI T1.403. No more than 15 consecutive zeros and at least N ones in each and
every time window of 8 x (N + 1) bits, where N = 1 through 23. When this bit is set to one, the DS26504 forces the transmitted
stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to
zero, as B8ZS encoded data streams cannot violate the pulse-density requirements.
0 = disable transmit pulse-density enforcer
1 = enable transmit pulse-density enforcer
Bit 3: Transmit AIS-CI Enable (TAIS-CI). Setting this bit causes the AIS-CI code to be transmitted from the framer to the
LIU, as defined in ANSI T1.403.
0 = do not transmit the AIS-CI code
1 = transmit the AIS-CI code
Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit
position.
0 = do not transmit the ESF RAI-CI code
1 = transmit the ESF RAI-CI code