Rainbow Electronics DS26504 - Manual (Page 3)

DS26504 T1/E1/J1/64KCC BITS Element
3 of 128
8. T1 FRAMER/FORMATTER CONTROL REGISTERS
......................................... 39
8.1 T1 C ONTROL R EGISTERS ......................................................................................................... 39
9. E1 FRAMER/FORMATTER CONTROL REGISTERS
........................................ 45
9.1 E1 C ONTROL R EGISTERS ......................................................................................................... 45
9.2 E1 I NFORMATION R EGISTERS ................................................................................................... 48
10. I/O PIN CONFIGURATION OPTIONS
....................................................................... 52
11. T1 SYNCHRONIZATION STATUS MESSAGE
..................................................... 55
11.1 T1 B IT -O RIENTED C ODE (BOC) C ONTROLLER .......................................................................... 55
11.2 T RANSMIT BOC ....................................................................................................................... 55
11.3 R ECEIVE BOC ......................................................................................................................... 56
12. E1 SYNCHRONIZATION STATUS MESSAGE
..................................................... 64
12.1 S A /S I B IT A CCESS B ASED ON CRC4 M ULTIFRAME .................................................................... 64
12.1.1 Sa Bit Change of State......................................................................................................................... 65
12.2 A LTERNATE S A /S I B IT A CCESS B ASED ON D OUBLE -F RAME ........................................................ 76
13. LINE INTERFACE UNIT (LIU)
...................................................................................... 79
13.1 LIU O PERATION ....................................................................................................................... 80
13.2 LIU R ECEIVER ......................................................................................................................... 80
13.2.1 Receive Level Indicator........................................................................................................................ 80
13.2.2 Receive G.703 Section 10 Synchronization Signal ............................................................................. 81
13.2.3 Monitor Mode ....................................................................................................................................... 81
13.3 LIU T RANSMITTER ................................................................................................................... 81
13.3.1 Transmit Short-Circuit Detector/Limiter................................................................................................ 82
13.3.2 Transmit Open-Circuit Detector ........................................................................................................... 82
13.3.3 Transmit BPV Error Insertion ............................................................................................................... 82
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)........................................................... 82
13.4 MCLK P RE -S CALER ................................................................................................................ 82
13.5 J ITTER A TTENUATOR ................................................................................................................ 82
13.6 CMI (C ODE M ARK I NVERSION ) O PTION ..................................................................................... 83
13.7 LIU C ONTROL R EGISTERS ........................................................................................................ 84
13.8 R ECOMMENDED C IRCUITS ........................................................................................................ 92
13.9 C OMPONENT S PECIFICATIONS .................................................................................................. 94
14. LOOPBACK CONFIGURATION
.................................................................................. 98
15. 64KHZ SYNCHRONIZATION INTERFACE
............................................................ 99
15.1 R ECEIVE 64 K H Z S YNCHRONIZATION I NTERFACE O PERATION ...................................................... 99
15.2 T RANSMIT 64 K H Z S YNCHRONIZATION I NTERFACE O PERATION .................................................. 100
16. 6312KHZ SYNCHRONIZATION INTERFACE
..................................................... 101
16.1 R ECEIVE 6312 K H Z S YNCHRONIZATION I NTERFACE O PERATION ................................................ 101
16.2 T RANSMIT 6312 K H Z S YNCHRONIZATION I NTERFACE O PERATION .............................................. 101
17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
.............. 102
17.1 I NSTRUCTION R EGISTER ......................................................................................................... 106
17.2 T EST R EGISTERS ................................................................................................................... 107
17.3 B OUNDARY S CAN R EGISTER .................................................................................................. 107
17.4 B YPASS R EGISTER ................................................................................................................. 107