ST & T UPSD3212C - Manual (Page 80)

uPSD3212A, uPSD3212C, uPSD3212CV
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Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)
Table 69. Description of the UCON1 Bits
7 6 5 4 3 2 1 0
TSEQ1 EP12SEL TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
Bit Symbol R/W Function
7 TSEQ1 R/W
Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1)
This bit determines which type of data packet (DATA0 or DATA1) will be
sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. RESET clears this bit.
6 EP12SEL R/W
Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2)
This bit specifies whether the data inside the registers UDT1 are used for
Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2
USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1,
STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for
Endpoint 1, the USB responds with a NAK handshake packet. RESET
clears this bit.
5 TX1E R/W
Endpoint1 / Endpoint2 Transmit Enable.
This bit enables a transmit to occur when the USB Host Controller send
an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set.
Software should set the TX1E Bit when data is ready to be transmitted. It
must be cleared by software when no more data needs to be transmitted.
If this bit is '0' or TXD1F is set, the USB will respond with a NAK
handshake to any Endpoint 1 or Endpoint 2 directed IN token.
RESET clears this bit.
4 FRESUM R/W
Force Resume.
This bit forces a resume state (“K” on non-idle state) on the USB data
lines to initiate a remote wake-up. Software should control the timing of
the forced resume to be between 10ms and 15ms. Setting this bit will not
cause the RESUMF Bit to set.
3 to 0
TP1SIZ3 to
TP1SIZ0
R/W The number of transmit data bytes. These bits are cleared by RESET.