ST & T UPSD3212C - Manual (Page 132)

uPSD3212A, uPSD3212C, uPSD3212CV
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LU. 3 complementary static tests are required on
10 parts to assess the latch-up performance. A
supply overvoltage (applied to each power supply
pin) and a current injection (applied to each input,
output, and configurable I/O pin) are performed on
each sample. This test conforms to the EIA/JESD
78 IC Latch-up Standard (see Table
108 ). For
more details, refer to the Application Note,
AN1181.
DLU. Electro-static discharges (one positive then
one negative test) are applied to each pin of 3
samples when the micro is running to assess the
latch-up performance in dynamic mode. Power
supplies are set to the typical values, the oscillator
is connected as near as possible to the pins of the
micro, and the component is put in reset mode.
This test conforms to the IEC 1000-4-2 and
SAEJ1752/3 Standards (see Table
108 ). For more
details, refer to the Application Note, AN1181.
Table 108. Latch-up and Dynamic Latch-up Electrical Sensitivities
Note: 1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications.
This means when a device belongs to “Class A,” it exceeds the JEDEC standard. “Class B” strictly covers all of the JEDEC criteria
(International standards).
Symbol Parameter Conditions
Level/
Class (1)
LU Static Latch-up Class T
A
= 25°C A
DLU Dynamic Latch-up Class V
DD
= 5V; T
A
= 25°C; f
OSC
= 40MHz A