ST & T UPSD3212C - Manual (Page 121)

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uPSD3212A, uPSD3212C, uPSD3212CV
External Chip Select
The CPLD also provides two External Chip Select
(ECS1-ECS2) outputs on Port D pins that can be
used to select external devices. Each External
Chip Select (ECS1-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure
64 .)
Figure 64. Port D External Chip Select Signals
PLD INPUT BUS
POLARITY
BIT
PD2 PIN PT2
ECS2
DIRECTION
REGISTER
ENABLE (.OE)
POLARITY
BIT
PD1 PIN PT1
ECS1
ENABLE (.OE)
DIRECTION
REGISTER
CPLD AND ARRAY
AI06607