ST & T UPSD3212C - Manual (Page 77)

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uPSD3212A, uPSD3212C, uPSD3212CV
Table 62. USB Interrupt Enable Register (UIEN: 0E9h)
Table 63. Description of the UIEN Bits
7 6 5 4 3 2 1 0
SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI
Bit Symbol R/W Function
7 SUSPNDI R/W Enable SUSPND Interrupt
6 RSTE R/W
Enable USB Reset; also resets the CPU and PSD Modules when bit is
set to '1.'
5 RSTFIE R/W Enable RSTF (USB Bus Reset Flag) Interrupt
4 TXD0IE R/W Enable TXD0 Interrupt
3 RXD0IE R/W Enable RXD0 Interrupt
2 TXD1IE R/W Enable TXD1 Interrupt
1 EOPIE R/W Enable EOP Interrupt
0 RESUMI R/W Enable USB Resume Interrupt when it is the Suspend Mode