Pld power management, Psd chip select input (csi, pd2), Input clock – ST & T UPSD3212C User Manual

Page 124: Input control signals, Table 99. power management mode registers pmmr0

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Pld power management, Psd chip select input (csi, pd2), Input clock | Input control signals, Table 99. power management mode registers pmmr0 | ST & T UPSD3212C User Manual | Page 124 / 163

This manual is related to the following products:

UPSD3212CV UPSD3212A