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Figure 17. mac gmii interconnect, 1 gmii signal multiplexing, 2 gmii interface signal definition – Intel IXF1104 User Manual

Page 94: Gmii signal multiplexing, Gmii interface signal definition, Mac gmii interconnect

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Intel

®

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

94

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

5.3.1

GMII Signal Multiplexing

The GMII balls are reassigned when using the RGMII mode or fiber mode.

Table 16 “Line Side

Interface Multiplexed Balls” on page 58

specifies the multiplexing of GMII balls in these modes.

See

Section 5.1.3, “Mixed-Mode Operation” on page 75

for proper configuration of the IXF1104

MAC in GMII mode.

5.3.2

GMII Interface Signal Definition

Table 26 “GMII Interface Signal Definitions” on page 95

provides the GMII interface signal

definitions. For information on 1000BASE-T GMII transmit and receive timing diagrams and
tables, please refer to

Table 49 “GMII 1000BASE-T Transmit Signal Parameters” on page 142

,

Figure 38 “1000BASE-T Transmit Interface Timing” on page 142

,

Figure 39 “1000BASE-T

Receive Interface Timing” on page 143

, and

Table 50 “GMII 1000BASE-T Receive Signal

Parameters” on page 143

Figure 17. MAC GMII Interconnect

TXC_3:0

TX_EN_3:0

TX_ER_3:0

RXC_3:0

TXD[7:0]_0

TXD[7:0]_3

TXD[7:0]_2

TXD[7:0]_1

RX_EN_3:0

RX_ER_3:0

RXD[7:0]_0

RXD[7:0]_3

RXD[7:0]_2

RXD[7:0]_1

COL_3:0

CRS_3:0

Intel

®

I

X

F1104

Medi

a A

c

cess Controller

TXC_3:0

TX_EN_3:0

TX_ER_3:0

TXD[7:0]_0

TXD[7:0]_3

TXD[7:0]_2

TXD[7:0]_1

RXC_3:0

RX_EN_3:0

RX_ER_3:0

RXD[7:0]_0

RXD[7:0]_3

RXD[7:0]_2

RXD[7:0]_1

COL_3:0

CRS_3:0

Quad PHY Device

B3203-01