2 disable and enable port sequences, 1 disable port sequence, 2 enable port sequence – Intel IXF1104 User Manual
Page 131: Disable and enable port sequences 6.2.1, Disable port sequence, Enable port sequence, Section 6.2, “disable and enable port sequences

Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
131
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Enable packet padding and CRC appending on transmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 0x0.
b. Fiber Mode:
Write the reserved bits to the default value.
Enable Packet padding and CRC Appending on transmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 1 to enable auto-negotiation.
Set bit 5 to 0 to enable forced mode operation.
13. Assert (set to 1)
14. Wait 1 to 2
μs.
15. Perform additional device configurations, as needed.
6.2
Disable and Enable Port Sequences
Intel recommends the following sequences to disable and enable individual ports, and for dropped
links. When a link is dropped, Intel recommends the port be completely reset and flushed to
remove packet fragments that may interfere with the auto-negotiation process on link recovery.
6.2.1
Disable Port Sequence
Use the following sequence to disable an individual port:
1. Disable the port using MAC port enable/disable bits [
Bits (3-0)].
2. Apply TX FIFO soft reset [
Bits(3-0)].
3. Introduce some delay to allow completion of packet transmission (not necessary if link is
dropped).
4. Flush TX [
“Flush TX ($ Port_Index + 0x11)”
Bit 0].
5. Apply MAC soft reset [
Bits(3-0)].
6. Apply RX FIFO soft reset [
Bits(3:0)].
6.2.2
Enable Port Sequence
Use the following sequence to enable an individual port:
1. Enable the port(s) using MAC port enable/disable bits [
Bits (3-0)].
2. Disable TX FIFO soft reset [
Bits(3-0)].
3. Reset flush TX [
“Flush TX ($ Port_Index + 0x11)”
Bit 0].
4. Disable MAC soft reset [
Bits(3-0)].
5. Disable RX FIFO soft reset [
Bits(3:0)].