Intel IXF1104 - Manual (Page 178)

Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 178
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
8.4.3 MAC TX Statistics Register Overview
The MAC TX Statistics registers contain all the MAC transmit statistic counters and are cleared
when read. The software must poll these registers to accumulate values and to ensure that the
counters do not wrap. The 32-bit counters wrap after approximately 30 seconds.
Table 94 covers all four MAC ports TX statistics. Port_Index is the port number (0, 1, 2, or 3).
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 1 of 4)
Name Description Address Type 1 Default
OctetsTransmittedOK
Counts the bytes transmitted in all legal
frames. The count includes all bytes
from the destination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted. Any initial collided
transmission attempts before a
successful frame transmission do not
add to this counter.
Port_Index +
0x40
R 0x00000000
OctetsTransmittedBad
Counts the bytes transmitted in all bad
frames. The count includes all bytes
from the destination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted.
Late collision counted: The count is
close to the actual number of bytes
transmitted before the frame is
discarded.
Excessive collision counted: The count
is close to the actual number of bytes
transmitted before the frame is
discarded.
TX under-run counted: The count is
expected to match the number of bytes
actually transmitted before the frame is
discarded.
TX CRC error counted: All bytes not
sent with success are counted by this
counter.
Any initial collided transmission
attempts before a successful frame
transmission do not add to this counter.
Port_Index +
0x41
R 0x00000000
TxUCPkts
The total number of unicast packets
transmitted (excluding bad packets). Port_Index +
0x42
R 0x00000000
TxMCPkts
The total number of multicast packets
transmitted (excluding bad packets).
NOTE: This count includes pause
control packets, which are also
counted in the
TxPauseFrames Counter.
Thus, these types of packets
are counted twice. Take care
when summing register counts
for reporting MIB information.
Port_Index +
0x43
R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write