Intel IXF1104 - Manual (Page 60)

Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 60
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
TERR_0 TERR_0 A8
MPHY: Use TERR_0 as the TERR
signal.
SPHY: Each port has its own dedicated
TERR_n signal
GND TERR_1 K1
GND TERR_2 E11
GND TERR_3 J8
TSOP_0 TSOP_0 C7
MPHY: Use TSOP_0 as the TSOP
signal.
SPHY: Each port has a dedicated
TSOP_n signal.
GND TSOP_1 E3
GND TSOP_2 C10
GND TSOP_3 J5
TEOP_0 TEOP_0 A7
MPHY: Use TEOP_0 as the TEOP
signal.
SPHY: Each port has a dedicated
TEOP_n signal.
GND TEOP_1 F3
GND TEOP_2 E4
GND TEOP_3 H5
TMOD[1:0] GND D9 A6
TSX and TMOD[1:0] are only applicable
in MPHY mode.
TSX GND E1
TADR[1:0] TADR[1:0] A12 A11 Used to address port for PTPA signal.
PTPA PTPA B11
PTPA can be used in MPHY and SPHY
modes.
DTPA_0:3 DTPA_0:3 D3 L1 A9 J7
DTPA is available on a per-port basis in
both MPHY and SPHY modes.
STPA NC C11 STPA is only applicable in MPHY mode.
RDAT[31:24] RDAT[7:0]_3
F24
G21 G24
G20 G23
G19 G22
G18
MPHY: Consists of a single 32 bit data
bus.
SPHY: Separate 8-bit data bus for each
Ethernet port.
RDAT[23:16] RDAT[7:0]_2
E21
C21 E22
C20 D22
B22 C22
B20
RDAT[15:8] RDAT[7:0]_1
F18
E16 E18
D16 E17
C17 F16
A17
RDAT[7:0] RDAT[7:0]_0
F14
C14 E14
B14 D14
A15 C13
A14,
RFCLK RFCLK A19
To achieve maximum bandwidth, set
RFCLK as follows:
MPHY: 133 MHz.
SPHY: 125 MHz.
RPRTY_0 RPRTY_0 E15
MPHY: Use RPRTY_0 as the RPRTY
signal.
SPHY: Each port has a dedicated
RPRTY_n signal.
NC RPRTY_1 G16
NC RPRTY_2 E20
NC RPRTY_3 F20
RENB_0 RENB_0 A13
MPHY: Use RENB_0 as the RENB
signal.
SPHY: Each port has a dedicated
RENB_n signal
VDD2 RENB_1 A18
VDD2 RENB_2 C19
VDD2 RENB_3 E24
Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)
SPI3 Signals
Ball Number Comments
MPHY SPHY