Table 73. collision distance ($ port_index + 0x05), Table 75. fc tx timer value ($ port_index + 0x07), Collision distance ($ port_index + 0x05) – Intel IXF1104 User Manual
Page 164: Collision threshold ($ port_index + 0x06), Fc tx timer value ($ port_index + 0x07), Fd fc address ($ port_index + 0x08 – + 0x09), Fc tx timer value
Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet
164
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Table 73. Collision Distance ($ Port_Index + 0x05)
Name
Description
Address
Type
1
Default
Collision
Distance
This is a 10-bit value that sets the limit for late
collision. Collisions happening at byte times
beyond the configured value are considered to be
late collisions. (Only valid in half-duplex).
Port_Index
+ 0x05
R/W
0x00000043
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 74. Collision Threshold ($ Port_Index + 0x06)
Name
Description
Address
Type
1
Default
Collision
Threshold
This is a 4-bit value that sets the limit for
excessive collisions. When the number of
transmission attempts performed for a packet
exceeds this value, it is considered to be an
excessive collision and the frame is dropped.
(Only valid in half-duplex).
Port_Index
+ 0x06
R/W
0x0000000F
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 75. FC TX Timer Value ($ Port_Index + 0x07)
Name
Description
Address
Type
1
Default
FC TX Timer
Value
The 16-bit pause length inserted in the flow
control pause frame sent to the receiving
station. The value is in 512-bit times.
Port_Index
+ 0x07
R/W
0x0000005E
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 76. FD FC Address ($ Port_Index + 0x08 – + 0x09)
Name
Description
Address
Type
1
Default
FD FC Address Low
The lowest 32 bits of the 48-bit globally
assigned multicast pause frame destination
address.
Port_Index
+ 0x08
R/W
0xC2000001
FD FC Address High
The highest 16 bits (47:32) of the globally
assigned multicast pause frame destination
address. The higher 16-bit address is
derived from bits 15:0 of this register.
Port_Index
+ 0x09
R/W
0x00000180
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write