Intel IXF1104 - Manual (Page 210)

Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 210
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630)
Name Description Address Type Default
Occupancy for Tx
FIFO Port 0 This register gives the Occupancy for TX FIFO
Port 0. This is a Read only register
0x62D R 0x00000000
Occupancy for Tx
FIFO Port 1 This register gives the Occupancy for TX FIFO
Port 1. This is a Read only register
0x62E R 0x00000000
Occupancy for Tx
FIFO Port 2 This register gives the Occupancy for TX FIFO
Port 2. This is a Read only register
0x62F R 0x00000000
Occupancy for Tx
FIFO Port 3 This register gives the Occupancy for TX FIFO
Port 3. This is a Read only register
0x630 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 141. TX FIFO Port Drop Enable ($0x63D)
Bit Name Description Type Default
Register Description: Independently enables the individual TX FIFOs to drop erroneous
packets.
0x0000000f
31:4 Reserved Reserved RO 0x000000
3 Port 3 Drop
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
R/W 1
2 Port 2 Drop
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
R/W 1
1 Port 1 Drop
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
R/W 1
0 Port 0 Drop
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
R/W 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write