Intel IXF1104 - Manual (Page 13)

Contents
Datasheet 13
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
170
Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [changed default value for the
register from “0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex)
from 1 to 0].
181
Modified Table 95 “PHY Control ($ Port Index + 0x60)” [added “Need one-sentence
descriptions of register” and register default value].
182
Modified Table 96 “PHY Status ($ Port Index + 0x61)” [added “Need one-sentence descriptions
of register” and register default value].
183
Modified Table 97 “PHY Identification 1 ($ Port Index + 0x62)” [added “Need one-sentence
descriptions of register” and register default value].
184
Modified Table 98 “PHY Identification 2 ($ Port Index + 0x63)” [added “Need one-sentence
descriptions of register” and register default value].
184
Modified Table 99 “Auto-Negotiation Advertisement ($ Port Index + 0x64)” [added “Need one-
sentence descriptions of register” and register default value].
185
Modified Table 100 “Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)”
[added “Need one-sentence descriptions of register” and register default value].
186
Modified Table 101 “Auto-Negotiation Expansion ($ Port Index + 0x66)” [added “Need one-
sentence descriptions of register” and register default value].
187
Modified Table 102 “Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)” [added “Need
one-sentence descriptions of register” and register default value].
211
Modified Table 143 “MDIO Single Read and Write Data ($0x681)” [changed MDIO write data to
“MDIO write data to external device”].
213
Modified Table 146 “SPI3 Transmit and Global Configuration ($0x700)” [changed default value
for bits 3:0 from “0” to “1” and changed default value for entire register from “0x0020000F” to
“0x00200000”].
215
Modified Table 147 “SPI3 Receive Configuration ($0x701)” [changed default value for bits 11:8
from “0xF” to “0x1”].
222
Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed default value for
bits 16:13 from “0xF” to “0x1”].
227
Added Figure 57 “FC-PBGA Package (Top and Bottom Views)” on page 227 and Figure 58
“FC-PBGA Mechanical Specifications” on page 228 .
229 Replaced Figure 59 “Package Marking Example” .
229 Added Section 9.4, “RoHS Compliance” on page 229 .
230
Added CBGA RoHS-compliant and FC-PBGA ordering information under Table 157 “Product
Information” .
Revision Number: 008
Revision Date: August 1, 2005 (Sheet 2 of 2)
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