3 per port registers, Figure 54. register overview diagram, 4 register map – Intel IXF1104 User Manual

Page 156: Per port registers, Register map, Register overview diagram, Mac control registers ($ port index + offset), Table 59

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Intel

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

156

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

8.3

Per Port Registers

Section 8.4

covers all of the registers that are replicated in each port of the IXF1104 MAC. These

registers perform an identical function in each port.

The address vector for the IXF1104 MAC is 11 bits wide. This allows for 7 bits of port-specific
access and a 4-bit vector to address each port and all global registers. The address format is shown
in

Figure 54

8.4

Register Map

Table 59

through

Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 162

present the

IXF1104 MAC memory map details. Global control and status registers are used to configure or
report on all ports, and some registers are replicated on a per-port basis.

Note:

All IXF1104 MAC registers are 32 bits.

Figure 54. Register Overview Diagram

Port Select & Global Registers

Per-Port Registers

Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)

Register

Bit Size

Mode

Ref Page

Offset

“Station Address ($ Port_Index +0x00 – +0x01)”