Intel IXF1104 - Manual (Page 4)

Contents
4 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
5.1.5.1 Speed..................................................................................................... 78
5.1.5.2 Duplex.................................................................................................... 78
5.1.5.3 Copper Auto-Negotiation ....................................................................... 78
5.1.6 Jumbo Packet Support .......................................................................................... 78
5.1.6.1
Rx Statistics ........................................................................................... 79
5.1.6.2 TX Statistics ........................................................................................... 79
5.1.6.3 Loss-less Flow Control........................................................................... 79
5.1.7 Packet Buffer Dimensions ..................................................................................... 80
5.1.7.1
TX and RX FIFO Operation ................................................................... 80
5.1.8 RMON Statistics Support....................................................................................... 80
5.1.8.1
Conventions ........................................................................................... 82
5.1.8.2 Advantages ............................................................................................ 83
5.2 SPI3 Interface ..................................................................................................................... 83
5.2.1
MPHY Operation.................................................................................................... 84
5.2.1.1
SPI3 RX Round Robin Data Transmission ............................................ 84
5.2.2 MPHY Logical Timing ............................................................................................ 84
5.2.2.1
Transmit Timing ..................................................................................... 85
5.2.2.2 Receive Timing ...................................................................................... 85
5.2.2.3 Clock Rates............................................................................................ 87
5.2.2.4 Parity...................................................................................................... 87
5.2.2.5 SPHY Mode ........................................................................................... 87
5.2.2.6 SPHY Logical Timing ............................................................................. 88
5.2.2.7 Transmit Timing (SPHY) ........................................................................ 88
5.2.2.8 Receive Timing (SPHY) ......................................................................... 88
5.2.2.9 SPI3 Flow Control .................................................................................. 91
5.2.3 Pre-Pending Function ............................................................................................ 93
5.3 Gigabit Media Independent Interface (GMII) ...................................................................... 93
5.3.1
GMII Signal Multiplexing ........................................................................................ 94
5.3.2 GMII Interface Signal Definition ............................................................................. 94
5.4 Reduced Gigabit Media Independent Interface (RGMII) .................................................... 96
5.4.1
Multiplexing of Data and Control............................................................................ 96
5.4.2 Timing Specifics..................................................................................................... 97
5.4.3 TX_ER and RX_ER Coding................................................................................... 97
5.4.3.1
In-Band Status ....................................................................................... 99
5.4.4 10/100 Mbps Functionality..................................................................................... 99
5.5 MDIO Control and Interface................................................................................................ 99
5.5.1
MDIO Address ..................................................................................................... 100
5.5.2 MDIO Register Descriptions ................................................................................ 100
5.5.3 Clear When Done ................................................................................................ 100
5.5.4 MDC Generation.................................................................................................. 100
5.5.4.1
MDC High-Frequency Operation ......................................................... 100
5.5.4.2 MDC Low-Frequency Operation .......................................................... 100
5.5.5 Management Frames........................................................................................... 101
5.5.6 Single MDI Command Operation......................................................................... 101
5.5.7 MDI State Machine .............................................................................................. 101
5.5.8 Autoscan Operation ............................................................................................. 103
5.6 SerDes Interface............................................................................................................... 103
5.6.1
Features............................................................................................................... 103
5.6.2 Functional Description ......................................................................................... 103
5.6.2.1
Transmitter Operational Overview ....................................................... 104
5.6.2.2 Transmitter Programmable Driver-Power Levels................................. 104