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Table 124. rx fifo overflow event ($0x5a0), 124 rx fifo overflow event ($0x5a0), Rx fifo overflow event ($0x5a0) – Intel IXF1104 User Manual

Page 197

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Intel

®

IXF1104 4-Port Gigabit Ethernet Media Access Controller

197

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

2

RX FIFO Errored
Frame Drop Enable
Port 2

This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable

0 = Frame Drop Disable

R/W

0

1

RX FIFO Errored
Frame Drop Enable
Port 1

This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable

0 = Frame Drop Disable

R/W

0

0

RX FIFO Errored
Frame Drop Enable
Port 0

This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable

0 = Frame Drop Disable

R/W

0

Table 124. RX FIFO Overflow Event ($0x5A0)

Bit

Name

Description

Type

1

Default

Register Description: This register provides a status if a FIFO-full situation occurs (for
example, a FIFO overflow). The bit position equals the port number. This register is cleared on
Read.

0x00000000

31:4

Reserved

Reserved

RO

0x0000000

3

RX FIFO Overflow
Event on Port 3

Port 3

0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred

R

0

2

RX FIFO Overflow
Event on Port 2

Port 2

0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred

R

0

1

RX FIFO Overflow
Event on Port 1

Port 1

0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred

R

0

0

RX FIFO Overflow
Event on Port 0

Port 0

0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred

R

0

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No

clear; R/W/C = Read/Write, Clear on Write

Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 2 of 2)

Bit

Name

Description

Type

1

Default

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No

clear; R/W/C = Read/Write, Clear on Write