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Figure 15. sphy receive logical timing, Sphy receive logical timing, Figure 15 “sphy receive logical timing – Intel IXF1104 User Manual

Page 89: Intel

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Intel

®

IXF1104 4-Port Gigabit Ethernet Media Access Controller

89

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Figure 15. SPHY Receive Logical Timing

LK

NB

OP

OP

R

AT

0]

TY

AL

B0

B2

B1

B62

B63

B0

B1