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Table 133, Table 133 “tx fifo low watermark – Intel IXF1104 User Manual

Page 204

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Intel

®

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

204

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005

Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)

Name

Description

Address

Type

1

Default

TX FIFO Low
Watermark Port 0

Low watermark for TX FIFO Port 0. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.

0x60A

R/W

0x000000D0

TX FIFO Low
Watermark Port 1

Low watermark for TX FIFO Port 1. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.

0x60B

R/W

0x000000D0

TX FIFO Low
Watermark Port 2

Low watermark for TX FIFO Port 2. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.

0x60C

R/W

0x000000D0

TX FIFO Low
Watermark Port 3

Low watermark for TX FIFO Port 3. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.

0x60D

R/W

0x000000D0

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No

clear; R/W/C = Read/Write, Clear on Write