Intel IXF1104 - Manual (Page 75)

Intel
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
75 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
5.1.3 Mixed-Mode Operation
The IXF1104 MAC gives the user the option of configuring each port for 10/100 Mbps half-duplex
copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This
gives the IXF1104 MAC the ability to support both copper and fiber operation line-side interfaces
operating at the same time within a single device. (Refer to
Figure 16 “Line Side Interface
Multiplexed Balls” on page 58 .)
The IXF1104 MAC provides complete flexibility in line-side connectivity by offering RGMII,
integrated SerDes, and GMII.
5.1.3.1 Configuration
The memory maps ( Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 156
through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 162 ) are logically split
into the following two distinct regions:
• Per-Port Registers
• Global Registers
To achieve a desired configuration for a given port, the relevant per-port registers must be
configured correctly by the user. The
Table 59 through Table 69 also contain registers that affect
the operation of all ports, such as the SPI3 interface configuration.
See Section 8.0, “Register Set” on page 155 for a complete description of IXF1104 MAC
configuration and status registers. The Register Maps ( Table 59 through Table 69 ) present a
summary of important configuration registers.
Note: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence”
on page 130 must be followed for proper configuration of the IXF1104 MAC.
5.1.3.2 Key Configuration Registers
The following key registers select the operational mode of a given port: