FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 9)

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CONTENTS
CHAPTER 1 FR FAMILY OVERVIEW .............................................................................. 1
1.1 Features of the FR Family CPU Core ................................................................................................. 2
1.2 Sample Configuration of an FR Family Device ................................................................................... 3
1.3 Sample Configuration of the FR Family CPU ..................................................................................... 4
CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 5
2.1 FR Family Memory Space .................................................................................................................. 6
2.1.1 Direct Address Area ...................................................................................................................... 7
2.1.2 Vector Table Area .......................................................................................................................... 8
2.2 Bit Order and Byte Order .................................................................................................................. 10
2.3 Word Alignment ................................................................................................................................ 11
CHAPTER 3 REGISTER DESCRIPTIONS ...................................................................... 13
3.1 FR Family Register Configuration ..................................................................................................... 14
3.2 General-purpose Registers ............................................................................................................... 15
3.3 Dedicated Registers ......................................................................................................................... 17
3.3.1 Program Counter (PC) ................................................................................................................. 18
3.3.2 Program Status (PS) ................................................................................................................... 19
3.3.3 Table Base Register (TBR) ......................................................................................................... 23
3.3.4 Return Pointer (RP) ..................................................................................................................... 25
3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) ............................................................. 27
3.3.6 Multiplication/Division Register (MD) ........................................................................................... 29
CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 31
4.1 Reset Processing .............................................................................................................................. 33
4.2 Basic Operations in "EIT" Processing ............................................................................................... 34
4.3 Interrupts ........................................................................................................................................... 37
4.3.1 User Interrupts ............................................................................................................................. 38
4.3.2 Non-maskable Interrupts (NMI) ................................................................................................... 40
4.4 Exception Processing ....................................................................................................................... 42
4.4.1 Undefined Instruction Exceptions ................................................................................................ 43
4.5 Traps ................................................................................................................................................. 44
4.5.1 "INT" Instructions ......................................................................................................................... 45
4.5.2 "INTE" Instruction ........................................................................................................................ 46
4.5.3 Step Trace Traps ......................................................................................................................... 47
4.5.4 Coprocessor Not Found Traps .................................................................................................... 48
4.5.5 Coprocessor Error Trap ............................................................................................................... 49
4.6 Priority Levels ................................................................................................................................... 51