FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E User Manual

Page 108

CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS

7.13

CMP2 (Compare Immediate Data and Destination Register)

Subtracts the result of the higher 28 bits of 4-bit immediate(from -16 to -1) data with
minus extension from the word data in "Ri", places results in the condition code
register (CCR).

■

CMP2 (Compare Immediate Data and Destination Register)

Assembler format:

CMP2 #i4, Ri

Operation:

Ri – extn(i4)

Flag change:

N :

Set when the MSB of the operation result is "1",cleared when the MSB is "0".

Z :

Set when the operation result is "0", cleared otherwise.

V :

Set when an overflow has occurred as a result of the operation, cleared otherwise.

C :

Set when a carry has occurred as a result of the operation, cleared otherwise.

Execution cycles:

1 cycle

Instruction format:

Example:

CMP2 #–3, R3

MSB

LSB

F F F F F F F D

N Z V C

CCR

0 0 0 0

N Z V C

0 1 0 0

F F F F F F F D

Instruction bit pattern :

1010 1001 1101 0011

Before execution

After execution