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2 non-maskable interrupts (nmi), Non-maskable interrupts (nmi) – FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E User Manual

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CHAPTER 4 RESET AND "EIT" PROCESSING

4.3.2

Non-maskable Interrupts (NMI)

Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests
can be produced when "NMI" external signal pin input to the microcontroller is active.
This section describes conditions for the acceptance of "NMI" interrupts, as well as
their operation and uses.

Overview of Non-maskable Interrupts

Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests can be produced

when "NMI" external signal pin input to the microcontroller is active.

Non-maskable interrupts cannot be disabled by the "I" flag in the condition code register (CCR) in the

program status (PS).

The masking function of the interrupt level mask register (ILM) in the "PS" is valid for "NMI". However, it

is not possible to use the software input to set "ILM" values for masking of "NMI", so that these interrupts

cannot be masked by programming.

Conditions for Acceptance of Non-maskable Interrupt Requests

The FR family CPU will accept an "NMI" request when the following conditions are met:

If "NMI" Pin Input is Active:

In normal operation: Detection of a negative signal edge

In stop mode:

Detection of an "L" level signal

If the "ILM" Value is Greater than 15.

Operation Following Acceptance of a Non-maskable Interrupt

When an "NMI" is accepted, the following operations take place:

(1) The contents of the "PS" are saved to the system stack.

(2) The address of the next instruction is saved to the system stack.

(3) The value of the system stack pointer (SSP) is reduced by 8.

(4) The value "15" is written to the "ILM".

(5) The value "0" is written to the "S" flag in "CCR" in the "PS".

(6) The value "TBR + 3C0

H

" is stored in the program counter (PC).

Time to Start of Non-maskable Interrupt Processing

The time required to start processing of an "NMI" can be expressed as a maximum of "n + 6" cycles from

the start of the instruction currently executing when the interrupt was received, where "n" represents the

number of execution cycles in the instruction.

If the instruction includes memory access, or insufficient instructions are present, the corresponding

number of wait cycles must be added.