FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 103)

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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.8 SUB (Subtract Word Data in Source Register from
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri".
■
SUB (Subtract Word Data in Source Register from Destination Register)
Assembler format: SUB Rj, Ri
Operation: Ri – Rj
→
Ri
Flag change:
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a borrow has occurred as a result of the operation, cleared otherwise.
Execution cycles: 1 cycle
Instruction format:
Example: SUB R2, R3
N Z V C
C C C C
MSB LSB
1 0 1 0 1 1 0 0 Rj Ri
R2
R3
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
N Z V C
CCR
R2
R3
CCR 0 0 0 0
N Z V C
1 0 0 0
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
Before execution After execution
Instruction bit pattern : 1010 1100 0010 0011