FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 306)

282
INDEX
Interlocking Produced by Reference to "R15" and
General-purpose Registers after Changing
the "S" Flag
.......................................... 57
Overview of General-purpose Registers ................ 15
Special Uses of General-purpose Registers ........... 15
H
Hazards
Overview of Register Hazards ............................. 56
I
ILM
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
............................................................ 19
Immediate Data
ADD (Add 4-bit Immediate Data to Destination
Register) ............................................... 73
ADD2 (Add 4-bit Immediate Data to Destination
Register) ............................................... 74
ADDN (Add Immediate Data to Destination Register)
............................................................ 77
ADDN2 (Add Immediate Data to Destination
Register) ............................................... 78
ADDSP (Add Stack Pointer and Immediate Data) 241
ANDCCR (And Condition Code Register and
Immediate Data) .................................. 238
BANDH (And 4-bit Immediate Data to Higher 4 Bits
of Byte Data in Memory) ..................... 108
BANDL (And 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory) ......................... 106
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory) ......................... 116
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory) ......................... 114
BORH (Or 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory) ......................... 112
BORL (Or 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory) ......................... 110
ORCCR (Or Condition Code Register and Immediate
Data) .................................................. 239
Indirect Address
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
.................................................. 209, 213
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
.......................................................... 225
DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
.......................................................... 219
Instruction
"INT" Instruction Operation ................................ 45
"INTE" Instruction Operation .............................. 46
"PC" Values Saved for "INT" Instruction Execution
............................................................ 45
"PC" Values Saved for "INTE" Instruction Execution
........................................................... 46
"PC" Values Saved for Undefined Instruction
Exceptions ........................................... 43
Examples of Processing Delayed Branching
Instructions .......................................... 61
Examples of Processing Non-delayed Branching
Instructions .......................................... 60
Examples of Programing Delayed Branching
Instructions .......................................... 62
General-purpose Registers during Execution of
"COPST/COPSV" Instructions ............... 48
How to Use Undefined Instruction Exceptions ...... 43
Instruction Formats ............................................ 64
Instruction Lists ............................................... 265
Instruction Notation Formats ............................... 66
Instructions Prohibited in Delay Slots .................. 58
Operations of Undefined Instruction Exceptions
........................................................... 43
Overview of Branching with Delayed Branching
Instructions .......................................... 58
Overview of Branching with Non-delayed Branching
Instructions .......................................... 58
Overview of the "INT" Instruction ....................... 45
Overview of the "INTE" Instruction ..................... 46
Overview of Undefined Instruction Exceptions ..... 43
Precautionary Information for Use of "INT"
Instructions .......................................... 45
Precautionary Information for Use of "INTE"
Instructions .......................................... 46
Restrictions on Interrupts during Processing of
Delayed Branching Instructions .............. 59
Symbols Used in Instruction Lists ..................... 263
Time to Start of Trap Processing for "INT"
Instructions .......................................... 45
Time to Start of Trap Processing for "INTE"
Instructions .......................................... 46
Time to Start of Undefined Instruction Exception
Processing ............................................ 43
Undefined Instructions Placed in Delay Slots ........ 43
Use of Operand Information Contained in Instructions
............................................................. 7
Instruction Execution
"PC" Values Saved for "INT" Instruction Execution
........................................................... 45
"PC" Values Saved for "INTE" Instruction Execution
........................................................... 46
Instruction Map
Instruction Map ............................................... 275
INT
"INT" Instruction Operation ................................ 45
"PC" Values Saved for "INT" Instruction Execution
........................................................... 45
INT (Software Interrupt) ................................... 188
Overview of the "INT" Instruction ....................... 45