FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 305)

281
INDEX
DMOVB (Move Byte Data from Register to Direct
Address) ............................................. 222
DMOVH
DMOVH (Move Half-word Data from Direct Address
to Post Increment Register Indirect Address)
.......................................................... 217
DMOVH (Move Half-word Data from Direct Address
to Register) ......................................... 215
DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
.......................................................... 219
DMOVH (Move Half-word Data from Register to
Direct Address) ................................... 216
E
E Format
"E" Format ...................................................... 276
EIT
Basic Operations in "EIT" Processing .................. 34
EIT handler
Recovery from EIT handler ........................... 28, 36
Emulator
INTE (Software Interrupt for Emulator) ............. 190
ENTER
ENTER (Enter Function) .................................. 254
Enter Function
ENTER (Enter Function) .................................. 254
EOR
EOR (Exclusive Or Word Data of Source Register to
Data in Memory) ................................. 100
EOR (Exclusive Or Word Data of Source Register to
Destination Register) ............................. 99
EORB
EORB (Exclusive Or Byte Data of Source Register to
Data in Memory) ................................. 104
EORH
EORH (Exclusive Or Half-word Data of Source
Register to Data in Memory) ................ 102
Error Information
Saving and Restoring Coprocessor Error Information
............................................................ 50
Error Trap
"PC" Values Saved for Coprocessor Error Traps
............................................................ 49
Conditions for Generation of Coprocessor Error Traps
............................................................ 49
Coprocessor Error Trap Operation ....................... 49
Overview of Coprocessor Error Traps .................. 49
Results of Coprocessor Operations after a Coprocessor
Error Trap ............................................ 49
Exception
"PC" Values Saved for Undefined Instruction
Exceptions ............................................ 43
Factors Causing Exception Processing ................. 42
How to Use Undefined Instruction Exceptions .......43
Operations of Undefined Instruction Exceptions ....43
Overview of Exception Processing .......................42
Overview of Undefined Instruction Exceptions ......43
Time to Start of Undefined Instruction Exception
Processing .............................................43
Exchange Byte Data
XCHB (Exchange Byte Data) ............................258
Exclusive Or Byte Data
EORB (Exclusive Or Byte Data of Source Register to
Data in Memory) .................................104
Exclusive Or Half-word Data
EORH (Exclusive Or Half-word Data of Source
Register to Data in Memory) .................102
Exclusive Or Word Data
EOR (Exclusive Or Word Data of Source Register to
Data in Memory) .................................100
EOR (Exclusive Or Word Data of Source Register to
Destination Register) ..............................99
Execution
"PC" Values Saved for "INT" Instruction Execution
............................................................45
"PC" Values Saved for "INTE" Instruction Execution
............................................................46
External Interrupts
Relation of Step Trace Traps to "NMI" and External
Interrupts ..............................................47
EXTSB
EXTSB (Sign Extend from Byte Data to Word Data)
..........................................................242
EXTSH
EXTSH (Sign Extend from Byte Data to Word Data)
..........................................................244
EXTUB
EXTUB (Unsign Extend from Byte Data to Word
Data) ..................................................243
EXTUH
EXTUH (Unsigned Extend from Byte Data to Word
Data) ..................................................245
F
Format
"E" Format .......................................................276
FR Family
Features of the FR Family CPU Core ......................2
FR Family Register Configuration ........................14
Sample Configuration of an FR Family Device ........3
Sample Configuration of the FR Family CPU ..........4
G
General-purpose Registers
General-purpose Registers during Execution of
"COPST/COPSV" Instructions ................48
Initial Value of General-purpose Registers ............16