FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 307)

283
INDEX
Precautionary Information for Use of "INT"
Instructions ........................................... 45
Time to Start of Trap Processing for "INT"
Instructions ........................................... 45
INTE
"INTE" Instruction Operation .............................. 46
"PC" Values Saved for "INTE" Instruction Execution
............................................................ 46
INTE (Software Interrupt for Emulator) ............. 190
Overview of the "INTE" Instruction ..................... 46
Precautionary Information for Use of "INTE"
Instructions ........................................... 46
Time to Start of Trap Processing for "INTE"
Instructions ........................................... 46
Interlocking
Interlocking ....................................................... 57
Interlocking Produced by Reference to "R15" and
General-purpose Registers after Changing
the "S" Flag
.......................................... 57
Interrupt
"PC" Values Saved for Interrupts ......................... 39
"PC" Values Saved for Non-maskable Interrupts
............................................................ 41
Conditions for Acceptance of Non-maskable Interrupt
Requests ............................................... 40
Conditions for Acceptance of User Interrupt Requests
............................................................ 38
How to Use Non-maskable Interrupts ................... 41
How to Use User Interrupts ................................. 39
INT (Software Interrupt) ................................... 188
INTE (Software Interrupt for Emulator) ............. 190
Interrupts during Execution of Stepwise Division
Programs .............................................. 37
Operation Following Acceptance of a Non-maskable
Interrupt ............................................... 40
Operation Following Acceptance of an User Interrupt
............................................................ 38
Overview of Interrupt Processing ........................ 37
Overview of Non-maskable Interrupts .................. 40
Overview of User Interrupts ................................ 38
Precautionary Information for Interrupt Processing in
Pipeline Operation ................................ 55
Relation of Step Trace Traps to "NMI" and External
Interrupts .............................................. 47
Restrictions on Interrupts during Processing of
Delayed Branching Instructions .............. 59
RETI (Return from Interrupt) ............................ 192
Sources of Interrupts .......................................... 37
Time to Start of Interrupt Processing .................... 39
Time to Start of Non-maskable Interrupt Processing
............................................................ 40
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
............................................................ 19
STILM (Set Immediate Data to Interrupt Level Mask
Register) ............................................ 240
J
JMP
JMP (Jump) .....................................................184
JMP:D (Jump) ..................................................196
Jump
JMP (Jump) .....................................................184
L
LD
LD (Load Word Data in Memory to Program Status
Register) .............................................157
LD (Load Word Data in Memory to Register)
.................150, 151, 152, 153, 154, 155
LDI
LDI:20 (Load Immediate 20-bit Data to Destination
Register) .............................................148
LDI:32 (Load Immediate 32-bit Data to Destination
Register) .............................................147
LDI:8 (Load Immediate 8-bit Data to Destination
Register) .............................................149
LDM
LDM0 (Load Multiple Registers) .......................246
LDM1 (Load Multiple Registers) .......................248
LDRES
LDRES (Load Word Data in Memory to Resource)
..........................................................227
LDUB
LDUB (Load Byte Data in Memory to Register)
..........................................162, 163, 164
LDUH
LDUH (Load Half-word Data in Memory to Register)
..........................................159, 160, 161
LEAVE
LEAVE (Leave Function) ..................................256
Leave Function
LEAVE (Leave Function) ..................................256
Left Direction
LSL (Logical Shift to the Left Direction) ....138, 139
LSL2 (Logical Shift to the Left Direction) ..........140
Load
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................231
Load Byte Data
LDUB (Load Byte Data in Memory to Register)
..........................................162, 163, 164
Load Half-word Data
LDUH (Load Half-word Data in Memory to Register)
..........................................159, 160, 161
Load Immediate
LDI:20 (Load Immediate 20-bit Data to Destination
Register) .............................................148
LDI:32 (Load Immediate 32-bit Data to Destination
Register) .............................................147