FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 73)

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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.5 Coprocessor Error Trap
A coprocessor error trap is generated when an error has occurred in a coprocessor
operation and the CPU executes another coprocessor instruction involving the same
coprocessor.
This section describes conditions for the generation, operations, and program counter
(PC) values saved of coprocessor error traps.
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Overview of Coprocessor Error Traps
A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU
executes another coprocessor instruction involving the same coprocessor. Note that no coprocessor error
traps are generated for execution of "COPSV" instructions.
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Conditions for Generation of Coprocessor Error Traps
A coprocessor error trap is generated when the following conditions are met.
• An error has occurred in coprocessor operation.
• A "COPOP/COPLD/COPST" instruction is executed involving the same coprocessor.
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Coprocessor Error Trap Operation
When a coprocessor error trap is generated, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the condition code register (CCR) in the "PS".
(5) The value "TBR + 3DC
H
" is stored in "PC".
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"PC" Values Saved for Coprocessor Error Traps
The "PC" value saved to the system stack represents the address of the next instruction after the
coprocessor instruction that caused the trap.
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Results of Coprocessor Operations after a Coprocessor Error Trap
Despite the occurrence of a coprocessor error trap, the execution of the coprocessor instruction ("COPOP/
COPLD/COPST") remains valid and the results of the instruction are retained. Note that the results of
operations affected by the coprocessor error will not be correct.