FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 303)

279
INDEX
Bit Patterns
Relation between Bit Patterns "Ri" and "Rj" and
Register Values ..................................... 64
BORH
BORH (Or 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory) ......................... 112
BORL
BORL (Or 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory) ......................... 110
Branch Relative
Bcc (Branch Relative if Condition Satisfied) ...... 194
Bcc:D (Branch Relative if Condition Satisfied)
.......................................................... 203
BTSTH
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
.......................................................... 119
BTSTL
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
.......................................................... 118
Bypassing
Register Bypassing ............................................. 56
Byte Order
Bit Order and Byte Order .................................... 10
C
CALL
CALL (Call Subroutine) ........................... 185, 186
CALL:D (Call Subroutine) ........................ 197, 199
Carry Bit
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 75
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register) ....... 80
CCR
Condition Code Register (CCR: Bit 07 to bit 00)
............................................................ 21
CMP
CMP (Compare Immediate Data of Source Register
and Destination Register) ....................... 83
CMP (Compare Word Data in Source Register and
Destination Register) ............................. 82
CMP2 (Compare Immediate Data and Destination
Register) .............................................. 84
Compare Immediate Data
CMP (Compare Immediate Data of Source Register
and Destination Register) ....................... 83
CMP2 (Compare Immediate Data and Destination
Register) .............................................. 84
Compare Word Data
CMP (Compare Word Data in Source Register and
Destination Register) ............................. 82
Condition Code Register
Condition Code Register (CCR: Bit 07 to bit 00)
............................................................ 21
COPLD
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................231
COPOP
COPOP (Coprocessor Operation) .......................229
Coprocessor
"PC" Values Saved for Coprocessor Error Traps
............................................................49
"PC" Values Saved for Coprocessor Not Present Traps
............................................................48
Conditions for Generation of Coprocessor Error Traps
............................................................49
Conditions for Generation of Coprocessor Not Found
Traps ....................................................48
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................231
COPOP (Coprocessor Operation) .......................229
Coprocessor Error Trap Operation ........................49
Coprocessor Not Found Trap Operation ................48
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................233
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................235
Overview of Coprocessor Error Traps ...................49
Overview of Coprocessor Not Found Traps ...........48
Results of Coprocessor Operations after a Coprocessor
Error Trap .............................................49
Saving and Restoring Coprocessor Error Information
............................................................50
COPST
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................233
General-purpose Registers during Execution of
"COPST/COPSV" Instructions ................48
COPSV
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................235
General-purpose Registers during Execution of
"COPST/COPSV" Instructions ................48
CPU
Features of the FR Family CPU Core ......................2
Initialization of CPU Internal Register Values at Reset
............................................................33
Sample Configuration of the FR Family CPU ..........4
D
Dedicated Registers
Dedicated Registers ............................................17
Delay Slots
Instructions Prohibited in Delay Slots ...................58
Undefined Instructions Placed in Delay Slots ........43
Delayed Branching Instructions
Examples of Processing Delayed Branching
Instructions ...........................................61