FUJITSU FR family 32-bit microcontroller instruction manuel CM71-00101-5E - Manual (Page 270)

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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.129 LDM0 (Load Multiple Registers)
The "LDM0" instruction accepts registers in the range R0 to R7 as members of the
parameter "reglist". (See Table 7.129-1.)
Registers are processed in ascending numerical order.
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LDM0 (Load Multiple Registers)
Assembler format: LDM0 (reglist)
Operation: The following operations are repeated according to the number of registers specified in the
parameter "reglist".
(R15)
→ Ri
R15 + 4
→ R15
Flag change:
N, Z, V, and C: Unchanged
Execution cycles: If "n" is the number of registers specified in the parameter "reglist", the execution cycles
re
q uired are as follows.
If n=0: 1 cycle
For other values of n: a (n – 1) + b + 1 cycles
Instruction format:
N Z V C
– – – –
Table 7.129-1 Bit Values and Register Numbers for "reglist" (LDM0)
Bit Register Bit Register
7 R7 3 R3
6 R6 2 R2
5 R5 1 R1
4 R4 0 R0
MSB LSB
1 0 0 0 1 1 0 0 reglist