Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 99)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
24-2
Bit 1: Amplifier 1 Enable (AMPEN1). This bit controls the active-high SHDNR output signal for the right-side motor
driver as follows:
0 = Disabled. SHDNR output is driven high.
1 = Enabled. SHDNR output is driven low to enable motor driver.
Bit 0: Amplifier 0 Enable (AMPEN0). This bit controls the active-high SHDNL output signal for the left-side motor
driver as follows:
0 = Disabled. SHDNL output is driven high.
1 = Enabled. SHDNL output is driven low to enable motor driver.
24.2.2 Op Amp Control Register (OPMCN, M3[0Ah])
Bits 7:4: Reserved. All reads return 0.
Bit 3: Op Amp D Enable (OPMEND). Setting this bit to 1 enables op amp D; setting this bit to 0 disables it. The OUTD
pin can still be used as an input to AIN5 even when the op amp is turned off.
Bit 2: Op Amp C Enable (OPMENC). Setting this bit to 1 enables op amp C; setting this bit to 0 disables it. The OUTC
pin can still be used as an input to AIN4 even when the op amp is turned off.
Bit 1: Op Amp B Enable (OPMENB). Setting this bit to 1 enables op amp B; setting this bit to 0 disables it. The OUTB
pin can still be used as an input to AIN3 even when the op amp is turned off.
Bit 0: Op Amp A Enable (OPMENA). Setting this bit to 1 enables op amp A; setting this bit to 0 disables it. The OUTA
pin can still be used as an input to AIN2 even when the op amp is turned off.
Bit # 7 6 5 4 3 2 1 0
Name — — — — OPMEND OPMENC OPMENB OPMENA
Reset 0 0 0 0 0 0 0 0
Access r r r r rw rw rw rw
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