Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 20)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
2-11
2.9.1 Divide-by-256 Mode (PMM)
In this power-management mode, all operations continue as normal, but at a reduced clock rate (the selected clock
source divided by 256).
This power-management mode is entered by setting the PMME bit (CKCN.2) to 1 and CD[1:0] to 0. When PMM mode
is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation reverts to divide-
by-1 mode.
2.9.2 Switchback Mode
As described in the MAXQ Family User’s Guide, switchback mode is used to provide an automatic exit from power-
management mode when a higher clock rate is required to respond to I/O, such as USART activity, SPI activity, or an
external interrupt.
Switchback mode is enabled when the SWB (CKCN.3) bit is set to 1 and the PMME (CKCN.2) bit is set to 1 (the system
is in the PMM mode). If switchback is enabled, the PMME bit is cleared (causing the system to exit power-management
mode) when any of the following conditions occur:
• An external interrupt condition occurs on an INTn pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the RX pin and the USART is enabled to receive data.
• The SBUF register is written to transmit a byte over the USART.
• The SPIB register is written to transmit a byte with the SPI interface enabled in master mode.
• The SSEL signal is asserted low with the SPI interface enabled in slave mode.
• A START condition occurs on the I
2 C bus and the I 2 C START interrupt is triggered.
• The supply voltage drops below the supply voltage monitor (SVM) threshold, and the SVM interrupt is triggered.
• An ADC conversion is initiated by setting ADCONV to 1.
• Active debug mode is entered either by a breakpoint match or direct issuance of the debug command from back-
ground mode.
As described in the MAXQ Family User’s Guide, if any of these conditions is true (a switchback source is active) and
the SWB bit has been set, the PMME bit cannot be set to enter power-management mode.
2.9.3 Stop Mode
Stop mode disables all clocked circuits within the MAXQ8913 and halts the processor completely. All on-chip clocks,
timers, serial ports, and other peripherals are stopped, and no code execution occurs. Once in stop mode, the
MAXQ8913 is in a near-static state, with power consumption determined largely by leakage currents.
Stop mode is invoked by setting the STOP bit to 1. The MAXQ8913 enters stop mode immediately when the STOP bit
is set. Entering stop mode does not affect the setting of the clock control bits; this allows the system to return to its
original operating frequency following stop mode removal.
The processor exits stop mode if any of the following conditions occur. In order to exit stop mode by means of an inter-
rupt, the interrupt must be enabled globally, by module, and locally prior to entering stop mode.
• External reset (from the RST pin)
• Power-on/brownout reset
• External interrupt
• I
2 C START interrupt
• Supply voltage monitor interrupt (SVMSTOP must be set to 1)
Note that exiting stop mode through external reset or power-on reset causes the processor to undergo a normal reset
cycle, as opposed to resuming execution at the point at which it entered stop mode. Exiting stop mode by means of an
interrupt causes the processor to vector to the interrupt handler routine at IV. Following the completion of the interrupt
handler, execution resumes at the instruction following the one that caused the entry into stop mode.
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