Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 18)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
2-9
2.8.1 Power-On Reset
When power is first applied to the MAXQ8913, or when the supply voltage at DVDD drops below the V RST level, the
processor is held in a power-on reset state. See Figure 2-6. For the MAXQ8913 to exit power-on reset, the following
two conditions must apply:
• The supply voltage at DVDD is above the power-on reset level V
RST
.
• The ring oscillator has completed a 10-cycle delay.
2.8.2 Watchdog Timer Reset
The watchdog timer on the MAXQ8913 functions as described in the MAXQ Family User’s Guide.
2.8.3 External Reset
External reset through the RST input is a synchronous reset source. After the external reset low has been removed and
sampled, execution resumes following a delay of four clock cycles, as shown in Figure 2-7.
Figure 2-6. Power-On Reset Timing
SUPPLY AT
V DVDD
V RST
1MHz
RING OSCILLATOR
INTERNAL
RESET
RGMD
T1
T2
T2 = 8192 EXTERNAL OSCILLATOR CYCLES
T1 = STARTUP TIME PLUS 10 RING OSCILLATOR CYCLES
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