Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 89)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
22-3
Bit 9: I 2 C Receiver Overrun Flag (I2CROI). This bit indicates a receive overrun when set to 1. This bit is set to 1 if
the receiver has already received two bytes since the last CPU read. This bit is cleared to 0 by software reading the
I2CBUF. Setting this bit to 1 by software causes an interrupt if enabled. Writing 0 to this bit does not clear the interrupt.
Bit 8: I
2 C General Call Interrupt Flag (I2CGCI). This bit is set to 1 when the general call is enabled (I2CGCEN = 1)
and the general call address is received. This bit must be cleared to 0 by software once set. Setting this bit to 1 by
software causes an interrupt if enabled.
Bit 7: I
2 C NACK Interrupt Flag (I2CNACKI). This bit is set to 1 if the I 2 C transmitter receives a NACK from the receiver.
Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software once set. This
bit is set by hardware only.
Bit 6: I
2 C Arbitration Loss Flag (I2CALI). This bit is set to 1 when the I 2 C is configured as a master and loses in the
arbitration. When the master loses arbitration, the I2CMST bit is cleared to 0. Setting this bit to 1 by hardware causes
an interrupt if enabled. This bit must be cleared to 0 by software once set. This bit is set by hardware only.
Bit 5: I
2 C Slave Address Match Interrupt Flag (I2CAMI). This bit is set to 1 when the I 2 C controller receives an
address that matches the contents in its slave address register (I2CSLA) during the address stage. This bit must be
cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
Bit 4: I
2 C Timeout Interrupt Flag (I2CTOI). This bit is set to 1 if either the I 2 C controller cannot generate a START
condition or the I 2 C SCL low time has expired the timeout value specified in the I2CTO register. This happens when
the I 2 C controller is operating in master mode and some other device on the bus is using the bus or holding SCL low
for an extended period of time. This bit must be cleared to 0 by software once set. Setting this bit to 1 by software
causes an interrupt if enabled.
Bit 3: I
2 C Clock Stretch Interrupt Flag (I2CSTRI). This bit indicates that the I 2 C controller is operating with clock
stretching enabled and is holding the SCL clock signal low. The I 2 C controller releases SCL after this bit has been
cleared to 0. Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software
once set. This bit is set by hardware only.
Bit 2: I
2 C Receive Ready Interrupt Flag (I2CRXI). This bit indicates that a data byte has been received in the I 2 C
buffer. This bit must be cleared by software once set. Setting this bit to 1 by hardware causes an interrupt if enabled.
This bit is set by hardware only.
Bit 1: I
2 C Transmit Complete Interrupt Flag (I2CTXI). This bit indicates that an address or a data byte has been suc-
cessfully shifted out and the I 2 C controller has received an acknowledgment from the receiver (NACK or ACK). This bit
must be cleared by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
Bit 0: I
2 C START Interrupt Flag (I2CSRI). This bit is set to 1 when a START condition (S or Sr) is detected. This bit
must be cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
22.1.3 I 2 C Interrupt Enable Register (I2CIE, M1[07h])
Bits 15:12, 10: Reserved. Read returns 0.
Bit 11: I
2 C STOP Interrupt Enable (I2CSPIE). Setting this bit to 1 causes an interrupt to the CPU when a STOP condi-
tion is detected (I2CSPI = 1). Clearing this bit to 0 disables the STOP detection interrupt from generating.
Bit # 15 14 13 12 11 10 9 8
Name — — — — I2CSPIE — I2CROIE I2CGCIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw r rw rw
Bit # 7 6 5 4 3 2 1 0
Name I2CNACKIE I2CALIE I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
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